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Hardware & Infrastructure

191 summarised stories in Hardware & Infrastructure, each linking back to the original source. Browse all topics →

Thursday, 5 March 2026

Bringing Robotics AI to Embedded Platforms: Dataset Recording, VLA Fine‑Tuning, and On‑Device Optimizations

Hugging Face Blog 4 months ago

NXP demonstrated how to deploy Vision-Language-Action (VLA) models on embedded robotic platforms by combining dataset recording practices, fine-tuning strategies, and hardware optimization. The team achieved 0.32-second inference latency on the i.MX 95 SoC for the ACT model (down from 2.86 seconds unoptimized) while maintaining 89% accuracy on a tea-bagging task across 30 test episodes. The approach decomposes VLA inference into separate vision, language, and action stages, applies selective quantization, and uses asynchronous scheduling to keep inference time below the action execution duration.

FlashAttention-4: Algorithm and Kernel Pipelining Co-Design for Asymmetric Hardware Scaling

Together AI 4 months ago

FlashAttention-4 is a new attention algorithm and kernel implementation that addresses asymmetric hardware scaling on Blackwell GPUs by pipelining tensor cores, special function units, and memory operations to reduce bottlenecks. The implementation achieves 1605 TFLOPs/s with 71% utilization on BF16, delivering 1.3× speedup over cuDNN and 2.7× over Triton by using software-emulated exponentials, tensor memory for intermediate storage, and 2-CTA MMA modes to reduce shared memory traffic. The design enables more efficient training and inference for large language models on next-generation hardware through careful co-optimization of algorithm and kernel implementation.

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