How OpenAI Used Its Own LLMs to Design Its Jalapeño Chip
IEEE Spectrum Matthew S. Smith
OpenAI says its first chip, Jalapeño, was built with help from its own AI models. That sped design up a lot, and the models are already getting better at the hard parts.
Based on reporting by IEEE Spectrum, Matthew S. Smith — read the original for the full story.
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OpenAI has finally shown off Jalapeño, its first AI accelerator chip, and the eye-catching part isn’t just the silicon. The company says the chip can hit up to 13.4 petaflops of 4-bit compute, uses 232 gigabytes of advanced memory, and links to that memory at 15.4 terabytes per second. OpenAI also says Jalapeño can cut end-to-end latency by as much as 3.6x versus Nvidia’s GB300, while using less power.
But the more interesting story is how fast it got there. Jalapeño went from first architecture idea to first silicon in under 20 months. Only nine months passed between the first RTL and tapeout. Richard Ho, OpenAI’s vice president of hardware, says the company’s models gave engineers “superpowers,” even if humans still made the final calls.
The team was small by chip-industry standards. Ho says it averaged fewer than 100 people during the project and sits at roughly 100 now as OpenAI works on second- and third-generation designs. OpenAI split the work with Broadcom: its own team handled end-to-end system design, including the accelerator, memory hierarchy and networking, while Broadcom took over the physical design from the gates onward.
OpenAI leaned heavily on tools that look more like software than traditional chip design. Its front-end workflow used XLS, an open-source high-level synthesis flow that lets engineers write in DSLX or C++ and then converts that code into Verilog. The company says that fit well with LLMs, which are better at software-like tasks. Chris Leary, who works on technical staff at OpenAI, says that helped because XLS itself “looks like software.”
The company didn’t stop at design. When the first chips came back from the foundry in May, OpenAI aimed its internal models at software optimization and says DeepSeek’s multi-head latent attention kernel benchmark jumped from 0.31 percent of the theoretical ceiling to 88.94 percent in about 40 hours. Ho says that kind of repeatable gain will shorten the gap between first silicon and full production ramps. OpenAI also says AI-guided physical design cut the matrix multiplication units’ area by 10 percent versus an optimized human baseline.
The models keep getting better too. Leary says the project started with help from models like o3, and later moved to precursors to GPT-6 Astra, which can work directly in Verilog and is nearing the point where it can operate proprietary design tools on its own. Ho says OpenAI also used internal chip-design models that aren’t public. The company isn’t claiming the whole job can be automated. It is claiming something narrower, and more useful: a small team, a fast loop, and a lot of AI where the work still looks suspiciously like code.
My take — AI-written commentary, not fact-checked reporting
This is the part of chip design that actually deserves the hype: not a robot designer replacing engineers, but a small team using models to grind through the boring, linguistic, iteration-heavy bits faster. The industry keeps talking about autonomy; OpenAI is talking about leverage. That’s the real pattern, and it’s much less flashy than the pitch decks.
Read more about this at: IEEE Spectrum