d-Matrix Adopts NVIDIA NVLink Fusion for Rack-Scale XPU Deployment
NVIDIA Blog Jesse Clayton
d-Matrix is plugging its next Raptor inference chips into NVIDIA’s rack-scale hardware. It’s a faster, lower-risk way to ship custom silicon without building the whole data center stack.
Based on reporting by NVIDIA Blog, Jesse Clayton — read the original for the full story.
Summary, retelling and take written by AI under human oversight; images are AI-generated illustrations. How we work · Report an error
d-Matrix is taking a shortcut — not in the chip design, but in everything around it. The inference chipmaker said it will use NVIDIA NVLink Fusion to hook its next-generation Raptor XPUs into NVIDIA’s AI infrastructure platform, alongside NVLink scale-up, Spectrum-X networking, the MGX rack architecture, and the wider NVIDIA AI stack.
That matters because the hard part of custom silicon is rarely just the silicon. It’s the rack, the networking, the power, the cooling, the software, the supply chain, the certification, and the endless integration work that turns a clever processor into something a customer can actually deploy. NVIDIA’s pitch is that NVLink Fusion lets partners skip a lot of that rebuild and lean on a platform that is already deployed at scale.
Sid Sheth, d-Matrix’s cofounder and CEO, framed it in practical terms during a press briefing yesterday: inference demand is rising, but money, time and energy are not. With NVLink Fusion and MGX, d-Matrix says it can bring Raptor XPUs into a liquid-cooled architecture and offer customers a faster path to ultralow-latency inference without taking on as much deployment risk.
And NVIDIA is making a broader play here. NVLink Fusion is meant to open the company’s infrastructure to third-party XPUs and CPUs, not just its own GPUs. The reference materials cite support for Arm, x86 and RISC-V, and list a growing partner set that includes d-Matrix, AWS, Arm, Intel, Fujitsu, SiFive, Alchip, Astera Labs, GUC, Marvell, MediaTek, Samsung, Cadence, Synopsys, Ayar Labs and Lightmatter.
The promise is simple: build the custom chip you want, then drop it into a common, validated AI factory instead of reinventing the rest of the machine. NVIDIA says that can cut XPU-to-XPU latency versus off-the-shelf Ethernet, raise packet rates, and give each XPU 3 TB/s of all-to-all bandwidth via sixth-generation NVLink. That is the real lure here — not openness for its own sake, but a way to make closed silicon play nicely inside someone else’s much bigger machine.
My take — AI-written commentary, not fact-checked reporting
This is what “open” looks like in NVIDIA country: you’re welcome to bring your own silicon, as long as you plug into NVIDIA’s furniture. For customers, that’s probably fine — fewer heroic integration stories, fewer expensive mistakes. For everyone else, it’s another reminder that the platform winner doesn’t need to own every chip; it just needs to own the door.
Read more about this at: NVIDIA Blog
