Hardware Architecture

2 summarised stories about Hardware Architecture, each linking back to the original source. Browse all topics →

Friday, 17 July 2026

Multibit neural inference in a N-ary crossbar architecture

arXiv cs.AI 6 hours ago

Researchers developed a simulation framework for in-memory computing using N-ary crossbar architectures with magnetic tunnel junctions to perform neural network inference directly in memory arrays. A 4x4 crossbar array with 4-state MTJs achieved 93.56% accuracy on MNIST classification compared to a 97.56% software baseline. Weight quantization emerged as the primary error source, and the study identified an optimal number of states per cell that minimizes total matrix-vector multiplication error while balancing quantization and resistance resolution tradeoffs.

AI Accelerators Hardware Architecture Neural Network Inference Quantization & Optimization

NIFA: Nonlinear IMC enhanced FPGA for efficient ML inference

arXiv cs.AI 6 hours ago

Researchers propose NIFA, an FPGA architecture with a ReRAM-based in-memory computing block that uses analog content-addressable memories instead of ADCs to perform nonlinear operations and dynamic matrix multiplication directly in hardware. The design achieves 40x higher energy efficiency on CNNs and 1.9x on Transformers compared to conventional approaches. This extends in-memory computing benefits to Transformer models that require frequent nonlinear operations, previously limited to static-weight models.

AI Accelerators Energy Efficiency Hardware Architecture ML Inference