IBM claims world's first sub-1 nanometer chip technology
Ars Technica ● Covered by 2 sources
IBM says it's built chip tech at a "sub-1 nanometer" node, stacking transistors to nearly double density on the same size chip. It's a naming trick more than a physical shrink, but the performance gains behind it look real.
Based on reporting by Ars Technica — read the original for the full story.
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IBM just unveiled something it's calling the world's first sub-1 nanometer chip technology, and the name alone is going to confuse people. Nobody is actually etching features smaller than a nanometer — that's not physically feasible with current materials. What IBM really built is a new transistor architecture, nicknamed "nanostack," that delivers the kind of performance jump you'd expect from a theoretical sub-1nm chip, even though the physical dimensions don't match the label. IBM calls it the 7 angstrom node, and yes, node numbers have been marketing shorthand rather than literal measurements for decades now.
The actual engineering is the interesting part. Nanostack takes IBM's existing nanosheet transistors — the tech behind its 2nm node from 2021 — and stacks two of them vertically in a staggered arrangement. Each transistor is built from three nanosheets, each just 5 nanometers thick, roughly 15 atoms of silicon stacked on top of each other, with about 9 nanometers of space between sheets. Cram that geometry efficiently enough and you get almost 100 billion transistors on a chip the size of a fingernail, according to IBM, which is roughly double the density of its previous generation.
IBM's own projections claim 50 percent higher compute performance or 70 percent better energy efficiency compared to its 2nm chips, depending on how a manufacturer tunes the tradeoff. There's also a separate win for SRAM, the fast but power-hungry memory type that AI accelerators depend on heavily. By staggering the channel design in SRAM bit cells, IBM says it shrank cell height by 40 percent, letting far more memory fit into the same footprint. That number matters because SRAM scaling has basically stalled in recent chip generations — Jay Gambetta, IBM Research's director, pointed out that the jump from 3nm to 2nm only bought a few percent of SRAM improvement. Getting 40 percent back is a genuinely big deal for anyone building AI hardware that's memory-bandwidth starved.
IBM doesn't manufacture chips itself, so this remains a research achievement until someone builds it at scale. The company's nanosheet work already became industry standard, adopted by Rapidus, Samsung, and independently by TSMC for their own 2nm processes, so there's precedent for IBM setting direction without owning production. IBM wouldn't name partners for nanostack specifically, but VP Huiming Bu expects commercial chips using it within five to ten years, eventually becoming the default architecture for CPUs and GPUs across the industry.
Whatever you call the node, the timing lines up with an AI industry that's desperate for more compute per watt. Data centers running large models are hitting power and cooling limits, and squeezing more transistors and memory into the same silicon without a bigger energy bill is exactly the kind of unglamorous hardware progress that ends up mattering more than the next flashy model release.
My take — AI-written commentary, not fact-checked reporting
The angstrom-node naming is silly marketing theater, but don't let that distract from the real story: IBM keeps setting the transistor roadmap that TSMC, Samsung, and everyone else eventually copies, without manufacturing a single commercial chip itself. That's a genuinely unusual position of influence, and it's the kind of unsexy infrastructure win that actually determines whether AI scaling keeps working, unlike whatever chatbot demo goes viral this week.
Read more about this at: Ars Technica